1. Field of the Invention
The present invention relates to a prefabricated, peripherally-leaded, semiconductor chip or die carrier having a reduced size, and methods for making and using the semiconductor die carrier. In a preferred embodiment, the semiconductor die carrier has horizontally and vertically spaced rows of multiple leads, with each lead being assembled into the semiconductor die carrier as an individually manufactured lead rather than a sub-element of a lead frame.
2. Description of the Related Art
There have been rapid advances in semiconductor technology, memory capacity, and software development in recent years. Advances in semiconductor packaging, interconnect technologies, and printed circuit board (PCB) assemblies have been more modest. The size of the semiconductor package and the number of leads it can accommodate are now major limiting factors determining computer speed and functionality. There is a trade-off between fabricating semiconductor packages with an increased number of leads and the resulting increase in component size. More leads mean a faster and more efficient transfer of information; however, more leads take up more space, thus increasing costs, and slowing down the electrical signal as it travels to interface with other devices.
With respect to semiconductor packages, many different shapes and sizes are currently available. Conventional semiconductor package technologies include the laminated ceramic technology, the pressed ceramic technology, and the molded plastic technology.
In accordance with the laminated ceramic technology, a semiconductor die is attached to a ceramic package having leads from a lead frame extending therefrom. Bonding pads on the die are connected to the leads using bonding wires. A cap is then glued to the ceramic package, thereby sealing the die and inner portions of the leads within the package.
In pressed ceramic technology, a semiconductor die is attached to a lower portion of a ceramic package having leads from a lead frame extending therefrom. After the wire bonding procedure, a top portion of the ceramic package is glued to the lower portion of the ceramic package to seal the die and inner portions of the leads within the package.
In molded plastic technology, a semiconductor die is configured for housing within a plastic package from which a set of leads will extend. In the initial stages of fabrication, the die is attached at a position surrounded by the leads from a lead frame. Wire bonding then takes place, and thereafter an injection molding process is carried out to form a plastic package within which the die and inner portions of the leads are sealed. The leads are then bent to form the finished package. The steps required to form a conventional molded plastic package may be understood more fully from the flowchart depicted in FIG. 1.
As can be understood from FIG. 2, conventional package leads are typically configured for mounting (on a PCB, for example) using plated-through-hole (PTH) technology or surface-mount technology (SMT).
In PTH technology, a conductive PTH is formed in a PCB. Each lead of a package is inserted through a corresponding PTH and then soldered to form a solder joint fastening the lead in conductive contact with the PTH.
In SMT mounting, each lead of a package, rather than being soldered to extend through a PTH in a PCB, is soldered onto a conductive portion of a top surface of the PCB. If the package is a leadless die carrier, a conductive section of the package is soldered onto a conductive portion of a top surface of the PCB known as a bonding pad. A solder joint then maintains each lead of the leaded die carrier, or each conductive section of the leadless die carrier, in a fastened relationship with respect to the PCB. In accordance with SMT mounting, each lead of a leaded die carrier can have a “Gullwing” configuration; “J-Lead” configuration; or a “Butt Lead” configuration.
Various conventional PTH and SMT packages are shown in FIG. 2. The PTH packages include a DIP (Dual In-line Package); an SH-DIP (Shrink DIP); an SK-DIP (Skinny DIP) or SL-DIP (Slim DIP); an SIP (Single In-line Package); a ZIP (Zig-zag In-line Package); and a PGA (Pin Grid Array). The SMT packages include an SO or SOP (Small Out-line Package); a QFP (Quad Flat Package); a LCC (Leadless Chip Carrier); and a PLCC SOJ (Plastic Leaded Chip Carrier with Butt Leads).
QFPs such as the ones shown in FIG. 2 are typically manufactured using the molded plastic technology described above. Most QFPs are manufactured using a single-layer lead frame providing a single row of bent leads extending from each of the four sides of the QFP.
Multi-row lead configurations are also known. For example, it is known to provide two rows of leads, formed by using two different lead frames vertically spaced and insulated from each other, extending from sides of a QFP. It is also known to provide rows of multiple leads formed using vertically spaced lead frames with adjacent rows of leads primarily separated from each other by a gaseous dielectric such as air. With respect to the wire bonding procedure associated with conventional semiconductor die packages, it is known in PGA packages to position bonding pads on different stepped levels.
The aforementioned semiconductor die packages suffer from many deficiencies. QFP technology, for example, is severely limited for a variety of reasons. For example, the molded plastic technology typically used to manufacture QFPs incorporates various processes following the wire bonding procedure which can have detrimental effects on the bonding integrity. These processes include s aling, which involves high-pressure injection-molding and cooling/heating steps, and the bending of the leads to achieve desired lead configurations, whereby bonding wire movement, breakage, and/or shorting can all result. Moreover, the encapsulation process is limited to the use of molding compounds with low thermal conductivity which can result in performances at less than an optimum level.
The use of lead frames during the manufacturing of QFP semiconductor packages and the like also results in numerous disadvantages. First of all, the types of dies from which conventional lead frames are stamped can be very expensive because of the number of intricate features involved and the amount of the material that must be handled. Moreover, the manufacturing tolerances required in stamping the larger sizes of necessary elements cause the stamping of lead frames to be a low-yield process. Also, packages which incorporate lead frames are typically tested after die placement at a point so late in the manufacturing process that if the package turns out to be defective, any value that may have been added is rendered useless. Additionally, lead frames typically limit the die placement process to procedures such as single-row peripheral pad bonding or tape automated bonding (TAB), thereby resulting in limitations in die placement options and flexibility. Furthermore, once a conventional QFP is completed, it is very difficult, if not impossible, to carry out repairs on one or more of the components of the package. In general, for conventional packaging technology, as the number of required leads increases, based on increases in the speed and functionality of the relevant die, so does the size of the lead frame, increasing its manufacturing and tooling costs and decreasing its efficiency due to the increased distances the signal must travel.
QFP-type packages also tend to take up large amounts of PCB area, due in part to the use of lead frames during their manufacture. For example, QFPs manufactured using a single-level lead frame and, therefore, including only a single row of leads extending from the sides of the QFP, typically require approximately 900 square millimeters of PCB area for a 208-pin QFP, and approximately 1,832 square millimeters of area for a 304-pin QFP.
Multi-row lead frame packages, to some extent, take up less PCB area in terms of the number of leads that can be provided. However, various limitations can render conventional multi-row leaded packages unsuitable for existing and contemplated packaging needs. Conventional structure, for example, is typically limited to two rows of leads per side, and all of the leads of both rows must be offset so that surface mounting can be performed in accordance with conventional mounting technology. Such characteristics can unnecessarily increase the amount of PCB area that will be required for mounting. Moreover, lead frames are typically used during the manufacture of the aforementioned conventional structure and, therefore, such structure is subject to a compounding of the inherent performance limitations and additional complexity, noted above.
PGA packages having a stepped configuration are also subject to limitations. For example, PGAs, unlike QFPS, are not generally suitable for SMT applications. Instead, PGAs are typically mounted using PTH technology or are plugged into a socket. Also, PGAs take up significant amounts of PCB space and space and volume of the PCB and, consequently, can be an impediment to the manufacture of high-density circuit configurations. Moreover, PGAs are typically expensive due to the cost of the ceramic package material and the brazed pin assembly that are used.
From the foregoing, it can be understood that conventional semiconductor packages take up large amounts of board space; are expensive and often experience difficulties during manufacture; perform insufficiently due to procedures carried out after chip attachment and wire bonding that tend to inhibit bond integrity; and, after manufacture, are difficult, if not impossible, to repair. As a result of such limitations, current semiconductor packaging technology is not sufficient to meet the needs of existing and/or future semiconductor and computer technology. Semiconductor packaging technology has already failed to keep pace with silicon die technology, and as computer and microprocessor speeds continue to climb, with space efficiency being increasingly important, semiconductor die packages having even smaller area requirements will be required. The semiconductor die packages discussed above fall short of current and contemplated semiconductor and computer requirements.